1. Field of the Invention
The present invention relates to a semiconductor memory device and more particularly to a circuit for designating an operating mode of the semiconductor memory device after the device is packaged.
The present application claims priority from Korean Application No. 8689/1995 which is incorporated herein by reference for all purposes.
2. Description of the Related Art
Semiconductor memory devices often have different operating modes. In the case of, for example, 64M DRAM, there are x1, x4, x8, x16, . . . , etc., according to the number of input/output pins, which is known as pin ratio mode, and there are 8K and 4K refresh cycles, which is known as the refresh cycle mode. There is also fast page mode, a static column mode, and an extended data out mode. Different operating modes may be implemented when the device is manufactured by designing different circuits for different semiconductor memory devices but this increases time and expense. It also becomes difficult to control stock of different type so semiconductor memory device. In order to solve the above problems, a method of designing semiconductor memory device has been utilized in which one chip has various operating modes which are selected by opening, or leaving closed, a fuse when the device is manufactured.
FIGS. 1A and 1B are views illustrating a construction of a conventional circuit for designating an operating mode of a semiconductor memory device which utilizes a fuse as discussed above. It is disclosed in U.S. Pat. No. 4,996,672 issued to the assignee of the present application, SAMSUNG Electronics Co., Ltd. FIG. 2 is a view illustrating wave forms generated by the circuits of FIGS. 1A and 1B. In FIG. 1B, a logic high or low state of a mode selection clock .PHI.M is maintained according to whether a fuse 121 is cut or not. The mode selection clock .PHI.M is a signal for enabling or disabling a certain operating mode of a semiconductor memory formed on the same substrate and as a part of the same process as that which formed the circuits of FIGS. 1A and 1B.
When an initial power supply voltage VCC is supplied, like signal 211 of FIG. 2, a power supply signal .PHI.VCC is generated, like signal 212 of FIG. 2. When the power supply signal .PHI.VCC changes from a logic low state to a logic high state, as does signal 212, a mode enabling signal .PHI.ME, signal 213 of FIG. 2, is generated by a pulse generating circuit shown in FIG. 1A. A pulse cycle of the mode enabling signal .PHI.ME is set by delay cycles of invertors 111, 112, 113. The mode enabling signal .PHI.ME is connected to a gate of an N-MOS transistor 122 in FIG. 1B. While a logic high state of mode enabling signal .PHI.ME is maintained, a turn-on state of an N-MOS transistor 122 is therefore also maintained.
At first, operation of the mode designating circuit of FIGS. 1A and 1B in a state which the fuse 121 is not cut will be described. While the logic high state of the mode enabling signal .PHI.ME is maintained, as shown in signal 213, a current flows through fuse 121 and N-MOS transistor 122. Assuming that a resistance of the fuse 121 is Rf and a turn-on resistance of the N-MOS transistor 122 is Rm, the voltage of a node 151 is maintained as VCC.times.Rm/(Rf+Rm). When the mode enabling signal .PHI.ME changes to the logic low state, the N-MOS transistor 122 turns off and the voltage of the node 151 increases to the power supply voltage VCC. When the voltage of the node 151 increases to the power supply voltage VCC, the logic state of a node 152 is changed into a logic low state by an invertor 123, thereby turning off the N-MOS transistor 124. Accordingly, the logic state of node 152 is latched into the logic low state by the invertor 123 and the N-MOS transistor 124, and as a result the mode selection clock .PHI.M goes a logic low state.
Next, operation of the mode designating circuit when fuse 121 is cut is described. While the logic high state of the mode enabling signal .PHI.ME is maintained, as shown in signal 213 of FIG. 2, the N-MOS transistor 122 is turned on. At this time, since the fuse 121 is cut, the current does not flow through the node 151. Accordingly, the potential of the node 151 is in a logic low state. When node 151 goes to the logic low state, the logic state of node 152 changes into a logic high state by invertor 123, thereby turning on the N-MOS transistor 124. Accordingly, the logic high state of the node 152 is maintained, and as a result the mode selection clock .PHI.M goes a logic high state.
The fuse 121 is cut by a laser prior to packaging the semiconductor memory device in the conventional mode selection circuit of FIGS. 1A and 1B. Accordingly, the operating mode of the semiconductor memory device can be selected only when it is in a wafer state. In other words, the operating mode cannot be designated after packaging of the semiconductor memory device because the fuse 121 must be cut by the laser prior to packaging. This creates several disadvantages. First, it is difficult to control the total stock for various product groups of the semiconductor memory device. In other words, when demand for semiconductor memory devices configured to operate in a certain mode increases, the memory devices must be configured with the laser, packaged and tested before the product can be shipped to a customer. Also, if an expected demand for the semiconductor memory devices configured in a certain operating mode is not exact or if demand suddenly changes, the semiconductor memory device having the operating mode of interest can be over-supplied or under-supplied.
Second, there is a disadvantage in that product yields are less when the operating mode is designated before packaging. Even though a semiconductor memory device does not pass s test for a specific operating mode, it might operate satisfactorily in other operating modes. When, however, the operating mode of the semiconductor memory device is designated in the wafer state thereof, the designated operating mode cannot be converted into any other operating modes after packaging.